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| AS1543/44 8 / 4 - C h a n n e l , 1 M s ps , 1 2 - B i t A D C w i t h S e q u e n c e r D a ta S he e t 1 General Description The AS1543/44 is a 12-bit high-speed, low-power, 8/4channel, successive-approximation ADC that operates from a single 2.7 to 5.25V supply. The device features high throughput rates (1Msps) and a low-noise, widebandwidth track-and-hold amplifier that can handle input frequencies in excess of 1 MHz. The AS1543 features 8 single-ended or 4 fully differential analog inputs while the AS1544 offers 4 singleended or 2 fully differential analog inputs. Both include a channel sequencer to allow a programmed selection of channels to be converted sequentially. The conversion time is determined by the SCLK frequency (also used as the master clock to control the conversion). The conversion process and data acquisition are controlled using a chip select pin and a serial clock signal, allowing the device to easily interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CSN and conversion is also initiated at this point. There are no pipeline delays associated with the device. The AS1543/44 uses advanced design techniques to achieve very low power dissipation at high throughput rates. At maximum throughput rates, the AS1543/44 consumes just 2.8mA (@3.6V), and 3.5mA (@5.25V). By using internal control register, single-ended or fullydifferential conversion mode with different input ranges can be used with either straight binary or twos complement output coding. The device is available in a TQFN(4x4)-20 pin package. 2 Key Features ! Single Supply Operation with VDRIVE Function: 2.7 to 5.25V Fast Throughput Rate: 1 Msps Sequencer & Channel Counter Software-Configurable Analog Input Types: - 8/4-Channel Single-Ended - 4/2-Channel Fully-Differential Software-Configurable Input Range Low Power Consumption at Max Throughput Rates: - 10.1mW @ 1Msps (3.6V Supply) - 18.4mW @ 1Msps (5.25V Supply) ! ! ! ! ! ! ! ! Shutdown Mode Current: 0.5A Flexible Power/Serial Clock Speed Management Wide Input Bandwidth: 71dB SNR @ 50 kHz Input Frequency No Pipeline Delays High Speed SPI/QSPI/Microwire/DSP Interface TQFN(4x4)-20 Package ! ! ! 3 Applications The devices are ideal for remote sensors, data-acquisition and data-logging devices, pen-digitizers, process control, or any other space-limited A/D application with low power-consumption requirements. Figure 1. Typical Application VDD REFIN 8 Multiplexer VIN0:7 Track/ Hold 12-Bit ADC DGND AGND Sequencer GND AS1543 Control Logic SCLK DOUT DIN CSN VDRIVE www.austriamicrosystems.com Revision 1.00 1 - 29 AS1543/44 Data Sheet 1 General Description ................................................................................................................................ 1 2 Key Features .......................................................................................................................................... 1 3 Applications ............................................................................................................................................ 1 4 Pinout ..................................................................................................................................................... 3 Pin Assignments ..................................................................................................................................................... 3 Pin Descriptions ..................................................................................................................................................... 3 5 Absolute Maximum Ratings .................................................................................................................... 4 6 Electrical Characteristics ........................................................................................................................ 5 Timing Specifications .............................................................................................................................................. 8 7 Typical Operating Characteristics ........................................................................................................... 9 8 Detailed Description ............................................................................................................................. 12 Converter Operation ............................................................................................................................................. 12 Analog Input ......................................................................................................................................................... 13 Track/Hold ..................................................................................................................................................... 13 Control Register ................................................................................................................................................... 14 Analog Input Configuration ............................................................................................................................ Input Channel Selection ................................................................................................................................ Transfer Functions ........................................................................................................................................ Two's Complement Transfer Function ........................................................................................................... Power Mode Selection .................................................................................................................................. Sequencer Operation .................................................................................................................................... 15 15 16 16 17 17 Shadow Register .................................................................................................................................................. 18 Direct Conversion (SEQ = 0, SHADOW = 0) ................................................................................................ 18 Shadow Register Conversion (SEQ = 0, SHADOW = 1) .............................................................................. 19 Channel Counter Conversion (SEQ = 1, SHADOW = 1) ............................................................................... 20 Serial Interface ..................................................................................................................................................... 20 Power Modes ....................................................................................................................................................... 22 Normal Mode (PM1 = 1, PM0 = 1) ................................................................................................................ 22 Auto Shutdown (PM1 = 0, PM0 = X) ............................................................................................................. 23 Power vs. Throughput Rate .................................................................................................................................. 23 VDRIVE ................................................................................................................................................................ 24 External Reference ............................................................................................................................................... 24 9 Application Information ......................................................................................................................... 25 Initialisation ........................................................................................................................................................... 25 Grounding and Layout Considerations ................................................................................................................. 26 10 Package Drawings and Markings ....................................................................................................... 27 11 Ordering Information .......................................................................................................................... 28 www.austriamicrosystems.com Revision 1.00 2 - 29 AS1543/44 Data Sheet - P i n o u t 4 Pinout Pin Assignments Figure 2. Pin Assignments (Top View) 11 AGND 11 AGND 10 REFIN 9 VDD GND CSN DIN 8 7 6 N/C 1 DGND 2 DOUT 3 SCLK 4 VDRIVE 5 15 VIN4 14 VIN5 13 VIN6 12 VIN7 14 N/C 13 N/C VIN3 16 VIN2 17 VIN1 18 VIN0 19 N/C 20 N/C 1 DGND 2 DOUT 3 SCLK 4 VDRIVE 5 10 REFIN 9 VDD GND CSN DIN VIN3 16 VIN2 17 VIN1 18 VIN0 19 N/C 20 AS1543 8 7 6 AS1544 Pin Descriptions Table 1. Pin Descriptions Pin Number Pin Name Description Analog Inputs. 8/4 single-ended or 4/2 fully-differential analog input channels that are multiplexed into the track-and-hold circuitry. Input channels are selected by using address bits ADDR3:ADDR0 (page 14) of the control register. The address bits in conjunction with bits SEQ (page 14) and SHADOW (page 14) allow the sequence register to be programmed. The bit SE/FDN (page 14) of the control register selects single-ended or fully-differential conversion mode. In case of single-ended mode the input range can extend from [0V to VREFIN] or [0V to 2 x VREFIN]. In case of fully-differential mode the differential input range can extend from [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN]. Note: Unused inputs should be connected to AGND to avoid noise. Reference Input. An external reference must be applied to this input. The voltage range for the external reference is 2.5V 1% for specified performance. Serial Clock. Provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the ADC conversion process 2.7 to 5.25V Supply Input. For the [0V to 2 x VREFIN] range, VDD must be between 4.75 and 5.25V Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the AS1543/44 serial interface. VDRIVE VDD required. Digital Output. The ADC conversion result is provided serially on this output. Data bits are clocked out on the falling edge of SCLK. The data stream consists of four address bits indicating the corresponding conversion channel, followed by 12 bits of conversion data (MSB first). Output coding may be selected as straight binary or two's complement depending on the setting of bit CODING (page 14). Digital Input. Data is clocked into to the AS1543/44 control register on this input (see Control Register on page 14). Chip Select. Active low input. Initiates conversions and also is used to frame the serial data transfer. Analog Ground. Ground reference point for all analog circuitry. All analog input signals and any external reference signal should be referenced to pin AGND. Note: AGND, GND and DGND pins must be connected together. Digital Logic Ground. Ground reference point for the VDRIVE logic power supply input. VDRIVE should be decoupled to pin DGND. Supply Ground. Ground reference point for the VDD supply input. The supply input VDD should be decoupled to pin GND. Revision 1.00 3 - 29 VINx REFIN SCLK VDD (see Figure 2) VDRIVE DOUT DIN CSN AGND DGND GND www.austriamicrosystems.com 12 N/C 15 N/C AS1543/44 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 5 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter VDD to GND/ AGND/ DGND VDRIVE to GND/ AGND/ DGND VINx, REFIN to GND/ AGND/ DGND CSN, SCLK, DIN, DOUT to GND/ AGND/ DGND Input Current (any pin except VDD and VINx) JA Thermal Impedance Electro-Static Discharge Operating Temperature Range Storage Temperature Range Junction Temperature -40 -65 Min -0.3 -0.3 -0.3 -0.3 -10 Max +7 VDD + 0.3 VDD + 0.3 VDRIVE + 0.3 +10 30.8 1 +85 +150 +150 Units V V V V mA C/W kV C C C The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C "Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices". The lead finish for Pb-free leaded packages is matte tin (100% Sn). Comments Package Body Temperature +260 C www.austriamicrosystems.com Revision 1.00 4 - 29 AS1543/44 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics VDD = VDRIVE = 2.7 to 5.25V, REFIN = 2.5V, fSCLK = 20MHz (50% Duty cycle), VCMIN = VREFIN/2 (when SE/FDN = 0), TAMB = -40 to +85C. Typical values at TAMB = +25C and VDD = VDRIVE = 5.25V (unless otherwise specified). Table 3. Electrical Characteristics Symbol DC Accuracy Resolution INL DNL Integral Nonlinearity Differential Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Offset Error Offset Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Gain Error Gain Error Match Zero Code Error Zero Code Error Match Gain Error Gain Error Match Dynamic Specifications 50kHz sinewave input SINAD SNR THD SFDR SINAD SNR THD SFDR IMD Signal to Noise + Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Signal to Noise + Distortion Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Isolation Full Power Bandwidth fA = 40.1kHz, fB = 41.5kHz Second Order Terms Third Order Terms Bit RANGE = 0, bit SE/FDN = 0, bit CODING = 0 68 68.5 Bit RANGE = 1, bit SE/FDN = 1 71.2 71.8 -82 84 71 71.5 -83 73 85 -83 -91 -79 35 3.6 -71 dB dB dB dB dB dB dB dB dB dB MHz Bit SE/FDN = 0, bit CODING = 0 Bit RANGE = 0 Bit RANGE = 1 Bit SE/FDN = 1, bit CODING = 1 Bit RANGE = 0 Bit RANGE = 1 0.5 4 0.6 4 0.5 4 0.6 0.6 0.5 4 0.5 0.6 0.5 4 0.5 4 4 Straight Binary Output Coding; Guaranteed No Missed Codes to 12 Bits -0.95 12 1 +1.2 4 Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB Parameter Condition Min Typ Max Unit fIN = 400kHz @ 3dB @ 0.1dB www.austriamicrosystems.com Revision 1.00 5 - 29 AS1543/44 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol Conversion Rate tCONV Conversion Time Track-and-Hold Acquisition Time Throughput Rate Aperture Delay Aperture Jitter Analog Input Bit RANGE = 1 VINx Input Voltage Ranges Bit SE/FDN = 1 Bit RANGE = 0 Bit RANGE = 1 Bit RANGE = 0 Bit RANGE = 1 Bit SE/FDN = 0 Bit RANGE = 0 DC Leakage Current Input Capacitance Reference Input REFIN Input Voltage 1 Parameter Condition 16 SCLK Cycles, SCLK = 20MHz Min Typ Max 800 300 1 Unit ns ns Msps ns ps 4 50 0 0 -VREFIN/ 2 -VREFIN VREFIN/2 VREFIN -1 20 VREFIN 2x VREFIN VREFIN/ 2 VREFIN VDD VREFIN/ 2 VDD VREFIN +1 V VINx - VINy Differential Input Voltage Ranges Bit SE/FDN = 0 V VCMIN Input Common Mode Voltage V A pF 2.5V 1% for Specified Performance 1 VDD 1 V A k DC Leakage Current REFIN Input Impedance Digital Inputs: CSN, SCLK, DIN VIH VIL IIN CIN Input High Voltage Input Low Voltage Input Current, Input Capacitance VDRIVE - 0.2 VIN = 0V or VDRIVE -1 5 0.7 x VDRIVE fSAMPLE = 1Msps 44 V 0.3 x VDRIVE +1 V A pF Digital Output: DOUT VOH VOL Output High Voltage Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance Output Coding ISOURCE = 200A; VDD = 2.7 to 5.25V ISINK = 200A Bit WEAK/TRIN (page 14) set to 0 Bit WEAK/TRIN set to 0 Bit CODING (page 14) set to 1 Bit CODING set to 0 -1 10 Straight (natural) binary Two's complement V 0.4 +1 V A pF www.austriamicrosystems.com Revision 1.00 6 - 29 AS1543/44 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol VDD VDRIVE Parameter Input Supply Range DRIVE Range VDRIVE VDD Normal Mode (Static) Normal Mode (Operational); fS = Max Throughput Auto Shutdown Mode Normal Mode (Operational); fSCLK = 20MHz Auto Shutdown Mode (Static) VDD = 2.7 to 5.25V, SCLK On or Off VDD = 4.75 to 5.25V, fSCLK = 20 MHz VDD = 2.7 to 3.6V, fSCLK = 20 MHz fSAMPLE = 250ksps Static VDD = 4.75 to 5.25V VDD = 2.7 to 3.6V VDD = 4.75 to 5.25V VDD = 2.7 to 3.6V Condition Min 2.75 2.75 1.8 3.0 2.4 1.4 0.01 3.5 2.8 1.6 0.5 18.4 10.1 2.5 1.5 Typ Max 5.25 5.25 Unit V V mA mA mA mA A mW mW W W Power Requirements IDD Input Current Power Dissipation (see Power vs. Throughput Rate on page 23). 1. When bit RANGE = 0 and bit SE/FDN = 1, VREFIN must not be larger than VDD/2. www.austriamicrosystems.com Revision 1.00 7 - 29 AS1543/44 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Timing Specifications VDD = 2.7 to 5.25V, VDRIVE VDD, REFIN = 2.5V; TAMB = -40 to +85C (unless otherwise specified). Specifications based on load circuit shown in Figure 3 on page 8. Table 4. Symbol fSCLK tCP tQUIET tCSS tCSDOE tCSDOV tCL tCH tDOH tDOV tDOD tDS tDH tCSH tWAKEUP 15 20 5 20 1 0.4 tCP 0.4 tCP 10 50 50 Min 0.01 50 50 10 20 40 Typ Max 20 Unit MHz SCLK frequency ns ns ns ns ns ns ns ns ns ns ns ns ns s SCLK periode Minimum quiet time required between bus relinquish and next conversion start. CSN Fall to SCLK Fall Setup CSN Fall to DOUT Enabled. CSN Fall to DOUT Valid. SCLK Pulse Width Low. SCLK Pulse Width High. SCLK Fall to DOUT Hold. SCLK Fall to DOUT Valid. SCLK Fall to DOUT Disable. DIN to SCLK Fall Setup. DIN to SCLK Fall Hold. Sixteenth SCLK Fall to CSN Rise Hold. Power-up time from auto shutdown mode. Description Figure 3. Load Circuit for Digital Output Timing Specifications 200A IOL DOUT CLOAD 25pF 200A IOH VDD/2 Figure 4. Serial Interface Timing Diagram CSN tCONVERT SCLK tCSS tCH 1 tCSDOV tCSDOE DOUT Tri-State ADDR3 DIN ADDR2 tDS WRITE SEQ ADDR1 ADDR0 4 ID Bits ADDR3 ADDR2 2 3 4 tDOV DB11 DB10 tDH ADDR1 ADDR0 SE/FDN 5 6 tDOH DB3 DB2 12 13 B 14 tCL DB1 DB0 tDOD DC DC DC DC = Don't Care 15 16 tCSH tQUIET Tri-State www.austriamicrosystems.com Revision 1.00 8 - 29 AS1543/44 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VDD = 5.25V; VREF = 2.5V, CREF = 4.7F, RANGE=1, SE/FDN=1, TAMB = +25C (unless otherwise specified). Figure 5. Integral Nonlinearity vs. Digital Output Code Figure 6. Differential Nonlinearity vs. Digital Output Code 1 fSAMPLE = 1Msps 1 0.8 0.6 fSAMPLE = 1Msps 0.8 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 3072 4096 DNL (LSB) . 0.4 INL (LSB) . 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 3072 4096 Digital Output Code Digital Output Code Figure 7. FFT @ 50kHz; RANGE=1, SE/FDN=1 20 0 -20 fSAMPLE = 1Msps NFFT = 32768 SNR=72.1dB THD = -84.7dB SFDR = 86.2dB Figure 8. FFT @ 50kHz; RANGE=1, SE/FDN=0 20 0 -20 fSAMPLE = 1Msps NFFT = 32768 SNR=71.0dB THD = -85.5dB SFDR = 86.5dB FFT (dBc) . FFT (dBc) . -40 -60 -80 -100 -120 0 100 200 300 400 500 -40 -60 -80 -100 -120 0 100 200 300 400 500 Input Signal Frequency (kHz) Input Signal Frequency (kHz) Figure 9. ENOB vs. VREFIN; RANGE=1, SE/FDN=1 11.7 11.6 VDD = 5V VDD = 3V Figure 10. ENOB vs. Input Signal Frequency 11.8 11.7 11.6 VDD = 5.25V ENOB (Bit) . ENOB (Bit) . 11.5 11.4 11.3 11.2 11.1 11 11.5 11.4 11.3 11.2 11.1 11 VDD = 2.7V VDD = 3.6V VDD = 4.75V 1 2 3 4 5 10 100 1000 VREFIN (V) Frequency (kHz) www.austriamicrosystems.com Revision 1.00 9 - 29 AS1543/44 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 11. THD vs. Input Signal Frequency -55 -60 VDD = 3.6V VDD = 2.7V VDD = 4.75V Figure 12. SINAD vs. Input Signal Frequency 75 VDD = 5.25V SINAD (dB) . THD (dBc) . -65 -70 -75 -80 -85 70 VDD = 4.75V 65 VDD = 3.6V 60 VDD = 5.25V VDD = 2.7V -90 10 100 1000 55 10 100 1000 Frequency (kHz) Frequency (kHz) Figure 13. THD vs. Input Signal Frequency -60 -65 10Ohm 50Ohm 100Ohm 1kOhm Figure 14. SINAD vs. Input Signal Frequency 74 72 THD (dBc) . -70 -75 -80 -85 -90 10 100 1000 SINAD (dB) . 70 68 66 64 62 60 10 100 1 0Ohm 50Ohm 1 00Ohm 1 kOhm 1000 Frequency (kHz) Frequency (kHz) www.austriamicrosystems.com Revision 1.00 10 - 29 AS1543/44 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 15. Supply Current vs. Supply Voltage 3 Figure 16. Supply Current vs. Temperature 3.2 . Supply Current (mA) 2 Supply Current (mA) 4.7 5.2 2.5 fMAX . 3.1 3 Static 1.5 2.9 1 2.7 3.2 3.7 4.2 2.8 -40 -15 10 35 60 85 Supply Voltage (V) Tem perature (C) Figure 17. Shutdown Supply Current vs. VDD 10 9 Figure 18. Shutdown Supply Current vs. Temp. 50 Supply Current (nA) . 8 7 6 5 4 3 2 1 2.7 3.2 3.7 4.2 4.7 5.2 Supply Current (nA) . 40 30 20 10 0 -40 -15 10 35 60 85 Supply Voltage (V) Tem perature (C) Figure 19. Supply Current vs. Throughput Rate 10 Figure 20. PSRR vs. Supply Signal Frequency -60 -65 . Supply Current (mA) 1 PSRR (dB) . -70 -75 VDD = 5V 0.1 -80 -85 0.01 VDD = 3V 0.001 0.1 10 1000 -90 0 200 400 600 800 1000 Throughput Rate (ks ps ) Ripple Frequency (kHz) www.austriamicrosystems.com Revision 1.00 11 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n 8 Detailed Description The AS1543/44 is a fast, 8/4-channel, 12-bit, single-supply, A/D converter, which can be operated from a 2.7 to 5.25V supply. The AS1543/44 is capable of throughput rates of up to 1Msps when provided with a 20MHz clock. The AS1543/44 features on-chip track/hold, A/D converter, sequencer and a serial interface in a TQFN(4x4)-20 package. The AS1543/44 has 8/4 single-ended or 4/2 fully-differential input channels with a channel sequencer, allowing the selection of the sequence of channels the ADC can cycle through on (each consecutive CSN falling edge). The serial clock input accesses data from the AS1543/44, controls the transfer of data written to the ADC, and provides the clock source for the successive-approximation A/D converter. The analog input range for the AS1543/44 is [0 to VREFIN] or [0V to 2 x VREFIN] for 8/4 single ended input channels or [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN] for 4/2 fully differential input channels depending on the setting of bit RANGE (page 14) and SE/FDN (page 14). For the [0V to 2 x VREFIN] mode, the device must be operated from a 4.75 to 5.25V supply. The AS1543/44 provides flexible power management options (see bits PM1, PM0 (page 14) of the control register) for the best power performance for a given throughput rate. Converter Operation The AS1543/44 is a 12-bit successive approximation analog-to-digital converter based around a capacitive DAC. The AS1543/44 can convert analog input signals in the range [0V to VREFIN] or [0V to 2 x VREFIN] or [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN] . Figure 21 and Figure 22 show simplified diagrams of the ADC operation. The ADC circuitry is made up of control logic, SAR, and a capacitive DAC, which are used to redistribute fixed amounts of charge with the capacitive DAC to bring the comparator back into a balanced condition. Figure 21 shows the ADC during its acquisition phase. Sample switch and input switch are closed. The comparator is held in a balanced condition and the sampling capacitors CHOLD acquires the signal on the selected VINx channel. Figure 21. Data Acquisition REFIN CH0 CH1 CH2 CH3 CH4 CH5 CH7 AGND Analog Input Multiplexer Input Switch AIN+ CSWITCH 11pF CHOLD 13pF + -+ Sample Switch CHOLD 13pF -+ S&H and capacitive DAC RIN - Comparator Control Logic AS1543 Input Switch AINCSWITCH 11pF CSWITCH includes all parasitics AGND When a conversion is started (see Figure 22), sample switch and input switch opens causing the comparator to become unbalanced. The control logic and the capacitive DAC are used to redistribute fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is re-balanced, the conversion is complete. Control logic generates the ADC output code. See page 16 for the ADC transfer functions. www.austriamicrosystems.com Revision 1.00 12 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 22. Data Conversion REFIN CH0 CH1 CH2 CH3 CH4 CH5 CH7 AGND Analog Input Multiplexer Input Switch AIN+ CSWITCH 11pF CHOLD 13pF + -+ Sample Switch CHOLD 13pF -+ S&H and capacitive DAC RIN - Comparator Control Logic AS1543 Input Switch AINCSWITCH 11pF CSWITCH includes all parasitics AGND Analog Input Figure 23 shows an equivalent circuit of one analog input. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care should be taken to ensure that the analog input signal never exceeds the supply rails by more than 300mV. This will cause these diodes to become forward biased and start conducting current into the substrate. 10mA is the maximum current these diodes can conduct without causing irreversible damage to the AS1543/44. Figure 23. Equivalent Analog Input Circuit D1 VINX C1 4pF D2 R1 C2 20pF Open for Conversion; Closed for Track Capacitor C1 in Figure 23 is typically about 4pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on-resistance of a switch (track/hold switch) and also includes the on-resistance of the input multiplexer. The total resistance is typically about 400. Capacitor C2 is the ADC sampling capacitor and typically has a capacitance of 20pF. Track/Hold The Track/Hold stage enters hold mode on the falling edge of CSN. For AC applications, removing high frequency components from the analog input signal is recommended by use of an R/C low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op-amp will be a function of the particular application. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion that can be tolerated. The THD will increase as the source impedance increases, and performance will degrade (see Figure 13 on page 10). www.austriamicrosystems.com Revision 1.00 13 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Control Register The AS1543/44 control register is a 13-bit, write-only register. Data is loaded into the register from pin DIN on the falling edge of the SCLK signal. Data is transferred on pin DIN at the same time as the conversion result is read from the device. The data transferred on pin DIN corresponds to the AS1543/44 configuration for the next conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 13 falling clock edges (after CSN falling edge) is loaded to the control register. The control register bits are defined in Table 6. Table 5. 12-Bit Control Register Format 12 (MSB) WRITE 11 SEQ 10 ADDR3 9 ADDR2 8 ADDR1 7 ADDR0 6 PM1 5 PM0 4 3 2 1 0 (LSB) SHADOW WEAK/ TRIN RANGE CODING SE/FDN Table 6. Control Register Bit Definitions Bit Number Bit Name Description Determines if the subsequent 12 bits will be loaded to the control register. 1 = The subsequent 12 bits will be written to the control register. 0 = The subsequent 12 bits are not loaded to the control register and its contents are unchanged. This bit is used in conjunction with the SHADOW bit to control the sequencer (see Table 11 on page 17) and access the shadow register (see page 18). These four address bits and the bit SE/FDN are loaded at the end of the present conversion sequence, and select which single analog input or pair of input channels is to be converted in the next serial transfer. The selected input channel is decoded as shown in Table 8 on page 15. These bits also may select the final channel in a consecutive sequence as described in Table 11 on page 17. The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of data (see Serial Interface on page 20). The next channel to be converted on will be selected by the multiplexer on the 14th SCLK falling edge. These two power management bits set the mode of operation of the AS1543/ 44 (see Table 10 on page 17). This bit is used in conjunction with the SEQ bit to control the sequencer (see Table 11 on page 17) and access the shadow register (see page 18). This bit selects the state of pin DOUT upon completion of the current serial transfer. 1 = DOUT will be weakly driven to the channel address specified by bit ADDR3 of the subsequent conversion. 0 = DOUT will return to tri-state at the end of the serial transfer (see Serial Interface on page 20). This bit selects the analog input range to be used for the subsequent conversion. This results in conjunction with bit SE/FDN in 4 possible analog input ranges, as explained in Table 7 on page 15 This bit selects the type of output coding to be used for the conversion result. 1 = The output coding for the next conversion is straight binary. 0 = The output coding for the next conversion is twos complement. This bit selects in conjunction with the adress bits ADDR3:ADDR0 the input channels to be used (see Table 8 on page 15). 1 = 8/4 single-ended input channels 0 = 4/2 fully-differential channels 12 WRITE 11 SEQ 10:7 ADDR3:ADDR0 6, 5 4 PM1, PM0 SHADOW 3 WEAK/TRIN 2 RANGE 1 CODING 0 SE/FDN www.austriamicrosystems.com Revision 1.00 14 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Analog Input Configuration Table 7. Analog Input Configuration via bits RANGE and SE/FDN Analog Input Configuration 8/4-channel single-ended RANGE 1 0 1 0 SE/FDN 1 1 0 0 Comments VINx from [0V to VREFIN] VINx from [0V to 2xVREFIN] VINx - VINy from [-VREFIN/2 to +VREFIN/2] VINx - VINy from [-VREFIN to +VREFIN] 4/2-channel fully-differential Note: If bit RANGE = 0 and bit SE/FDN =1 VDD must be at least two times larger than VREFIN. Input Channel Selection The input channels for conversion are selected using control register bits ADDR3:ADDR0 and bit SE/FDN. Table 8. Channel Selection via Bits ADDR3:ADDR0 and SE/FDN, AS1544 ADDR3 X AS1544 X X X ADDR2 X X X X ADDR1 0 0 1 1 ADDR0 0 1 0 1 Analog Input Channel SE/FDN = 1 (Single-Ended) VIN0 VIN1 VIN2 VIN3 Analog Input Channel SE/FDN = 0 (Fully-Differential) VIN0 - VIN1 VIN1 - VIN0 VIN2 - VIN3 VIN3 - VIN2 Table 9. Channel Selection via Bits ADDR3:ADDR0 and SE/FDN, AS1543 ADDR3 X X X AS1543 X X X X X ADDR2 0 0 0 0 1 1 1 1 ADDR1 0 0 1 1 0 0 1 1 ADDR0 0 1 0 1 0 1 0 1 Analog Input Channel SE/FDN = 1 (Single-Ended) VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Analog Input Channel SE/FDN = 0 (Fully-Differential) VIN0 - VIN1 VIN1 - VIN0 VIN2 - VIN3 VIN3 - VIN2 VIN4 - VIN5 VIN5 - VIN4 VIN6 - VIN7 VIN7 - VIN6 www.austriamicrosystems.com Revision 1.00 15 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Transfer Functions Output coding and transfer function depend on the control register bits RANGE (page 14), SE/FDN (page 14) and CODING (page 14). Figure 24. Straight Binary Transfer Function for SE/FDN = 1 and CODING = 1 RANGE = 1; VREF=VREFIN RANGE = 0; VREF=2xVREFIN Full Scale = VREF Zero Scale = 0 1LSB = VREF/4096 Full Scale (FS) Transition Figure 25. Straight Binary Transfer Function for SE/FDN = 0 and CODING = 1 RANGE = 1; VREF=VREFIN RANGE = 0; VREF=2xVREFIN Full Scale = +VREF/2 Zero Scale = -VREF/2 1LSB = VREF/4096 Full Scale (FS) Transition 11...111 11...110 11....101 Output Code 11...111 11...110 11....101 Output Code 00...011 00...010 00...001 00...000 00...011 00...010 00...001 00...000 0 1 2 3 Input Voltage VINx (LSB) FS - 3/2LSB ZS ZS+1LSB FS - 3/2LSB Input Voltage VINx - VINy (LSB) Figure 26. Two's Complement Transfer Function for SE/FDN = 1 and CODING = 0 RANGE = 1; VREF=VREFIN RANGE = 0; VREF=2xVREFIN Full Scale = VREF -Full Scale = 0 Zero Scale = VREF/2 1LSB = VREF/4096 Figure 27. Two's Complement Transfer Function for SE/FDN = 0 and CODING = 0 RANGE = 1; VREF=VREFIN RANGE = 0; VREF=2xVREFIN Full Scale = +VREF/2 -Full Scale = -VREF/2 Zero Scale = 0 1LSB = VREF/4096 011....111 011...110 011....111 011...110 Output Code Output Code -FS ZS Input Voltage VINx (LSB) +FS - 1LSB 000...010 000...001 000...000 111...111 111...110 111...101 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 100...001 100...000 -FS ZS +FS - 1LSB Input Voltage VINx - VINy (LSB) www.austriamicrosystems.com Revision 1.00 16 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Power Mode Selection Control register bits PM1 and PM0 are used to configure the AS1543/44 power mode. Table 10. Power Mode Selection via Bits PM1 and PM0 PM1 1 PM0 1 Mode Description In this mode, the AS1543/44 remains in full power mode regardless of the Normal Operation status of any of the logic inputs. This mode allows the fastest possible throughput rate. In this mode, the AS1543/44 automatically enters shutdown mode at the end of each conversion when the control register is updated. Wake-up time from shutdown is 1s. Note: Ensure that 1s has elapsed before attempting to perform a valid conversion in this mode. 0 X Auto Shutdown Sequencer Operation The setting of control register bits SEQ and SHADOW sets the sequencer operation and also selects the shadow register for programming. Table 11. Sequencer Configuration via Bits SEQ and SHADOW SEQ SHADOW Description These settings indicate that the sequencer is not used. The analog input channel selected for each individual conversion is determined by the contents of the channel address bits ADDR3:ADDR0 (page 14) in each prior write operation. This mode of operation reflects the normal operation of a multi-channel ADC (without the sequencer) where each write to the AS1543/44 specifies the next input channel for conversion (see Figure 28 on page 18). These settings select the shadow register for programming. After a write to the control register, the following write operation will load the contents of the shadow register. This will program the sequence of channels to be repeatedly converted each successive valid CSN falling edge (see Table 12 on page 18 and Figure 29 on page 19). Note: The specified input channels need not be consecutive. With these settings, the sequencer will not be interrupted upon completion of a write operation. This allows other bits of the control register (PM1, PM0, WEAK/TRIN, RANGE, CODING and SE/FDN) to be altered while in a sequence without terminating the cycle. These settings are used in conjunction with the channel address bits ADDR3:ADDR0 to program continuous conversions on a consecutive sequence of channels (channel 0 ... channel n) as determined by the address bits ADDR3:ADDR0 (page 14) of the control register (see Figure 30 on page 20). 0 0 0 1 1 0 1 1 www.austriamicrosystems.com Revision 1.00 17 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Shadow Register The shadow register is a 16-bit, write-only register. Data is loaded from pin DIN of the AS1543/44 on the falling edge of SCLK. The data is transferred on pin DIN at the same time as a conversion result is read from the device. This requires 16 serial falling edges for the data transfer. The information is clocked into the shadow register (provided bits SEQ (page 14) and SHADOW (page 14) were set to 0, 1 respectively), in the previous write to the control register. Each bit represents one of the input channels (VIN0 through VIN3/VIN7). Multiple channels can be selected for continuous cycling on each consecutive CSN falling edge after a write to the shadow register. To select a sequence of channels, the associated bit must be set for each analog input channel. The AS1543/44 will continuously cycle through the selected channels in ascending order, beginning with the lowest channel, until a write operation occurs (i.e., bit WRITE (page 14) is set to 1) with bits SEQ and SHADOW configured in any way except 1, 0 (see Table 11 on page 17). Table 12. 16-Bit Shadow Register Format, AS1543 15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Table 13. 16-Bit Shadow Register Format, AS1544 15 (MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) VIN0 VIN1 VIN2 VIN3 VIN0 VIN1 VIN2 VIN3 VIN0 VIN1 VIN2 VIN3 VIN0 VIN1 VIN2 VIN3 Direct Conversion (SEQ = 0, SHADOW = 0) Figure 28 shows the normal flow of an ADC with multiple input channels selected, where each serial transfer selects the next channel for conversion. In this mode of operation, the sequencer function is not used. Figure 28. Bit SEQ = 0, Bit SHADOW = 0 Flowchart Power On CSN Falling Edge DOUT: Dummy Conversion Result DIN: Write to Control Register; Bit WRITE = 1; Select Coding, Range, SE/FDN, WEAK/TRIN and Power Mode; Select Channel ADDR3:ADDR0 (see Table 5 on page 14) for Conversion Bit SEQ = 0, Bit SHADOW = 0 Bit WRITE = 0 Bit WRITE = 1, Bit SEQ = 0, Bit SHADOW = 0 Bit WRITE = 1 Bit SEQ = 0 Bit SHADOW = 0 Bit WRITE = 0 CSN Falling Edge DOUT: Conversion Result from previously selected ADDR3:ADDR0 Channel DOUT: Conversion Result from previously selected ADDR3:ADDR0 Channel DIN: Write to Control Register; Bit WRITE = 1; Select Coding, Range, SE/FDN, WEAK/ TRIN and Power Mode; Select Channel ADDR3:ADDR0 for Conversion Bit SEQ = 0, Bit SHADOW = 0 Bit WRITE = 0 Bit WRITE = 1, Bit SEQ = 0, Bit SHADOW = 0 CSN Falling Edge Exit this flow whenever WRITE = 1 and NOT (SEQ = 0, SHADOW = 0) www.austriamicrosystems.com Revision 1.00 18 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Shadow Register Conversion (SEQ = 0, SHADOW = 1) Figure 29 shows how to program the AS1543/44 to continuously convert from a particular sequence of channels. To exit this mode of operation and revert back to the normal mode of operation of a multi-channel ADC (as outlined in Figure 28), verify bit WRITE (page 14) = 1 and bits SEQ and SHADOW = 0 on the next serial transfer. Note: If all 0s are written into the Shadow Register (see Table 12 on page 18) channel 3/7 will be chosen by default. Figure 29. Bit SEQ = 0, Bit SHADOW = 1 Flowchart Power On CSN Falling Edge DOUT: Dummy Conversion Result DIN: Write to Control Register; Bit WRITE = 1; Select Coding, Range, SE/FDN, WEAK/TRIN and Power Mode; Select Channel ADDR3:ADDR0 (see Table 5 on page 14) for Conversion Bit SEQ = 0, Bit SHADOW = 1 CSN Falling Edge DOUT: Conversion Result from previously selected ADDR3:ADDR0 Channel; DIN: Write to Shadow Register (see Table 12 on page 18) Selecting Channels for Conversion* Bit WRITE = 0 * Need not be consecutive channels. Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0 Bit WRITE = 0 Bit WRITE = 1 Bit SEQ = 1 Bit SHADOW = 0 CSN Falling Edge DOUT: Conversion Result from previously selected ADDR3:ADDR0 Channel Bit WRITE = 0 Continuously Convert the selected sequence of Channels CSN Falling Edge Exit this flow whenever WRITE = 1 and NOT (SEQ = 1, SHADOW = 0) Continuously Convert the selected sequence of Channels and allow Changes to Control Register without Conversion Interruption DOUT: Conversion Result from previously selected ADDR3:ADDR0 Channel Bit WRITE = 1 Bit SEQ = 1, Bit SHADOW = 0 www.austriamicrosystems.com Revision 1.00 19 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Channel Counter Conversion (SEQ = 1, SHADOW = 1) Figure 30 shows how a sequence of consecutive channels can be converted from without having to program the shadow register or write to the part on each serial transfer. To exit this mode of operation and revert back to the normal mode of operation of a multi-channel ADC (as outlined in Figure 29), verify bit WRITE (page 14) = 1 and bits SEQ and SHADOW = 0 on the next serial transfer. Figure 30. Bit SEQ = 1, Bit SHADOW = 1 Flowchart Power On CSN Falling Edge DOUT: Dummy Conversion Result DIN: Write to Control Register; Bit WRITE = 1; Select Coding, Range, SE/FDN, WEAK/TRIN and Power Mode Use ADDR3:ADDR0 (see Table 5 on page 14) for Channel Counter Conversion* Bit SEQ = 1, Bit SHADOW = 1 Bit WRITE = 0 *The binary selected channel number will determine the last channel used for conversion. e.g.: 0101 = 5 => channel 0:5 will be used for conversion. Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0 Bit WRITE = 1 Bit SEQ = 1 Bit SHADOW = 0 Bit WRITE = 0 DOUT: Conversion Result from previously selected Channel Bit WRITE = 0 Continuously Convert Consecutive Sequence of Channels from Channel 0 up to and including Previously Selected ADDR3:ADDR0 in the Control CSN Falling Register Edge DOUT: Conversion Result from previously selected Channel Continuously Convert the Selected Sequence of Channels and Allow Changes to Control Register without Conversion Interruption Bit WRITE = 1, Bit SEQ = 1, Bit SHADOW = 0 CSN Falling Edge Exit this flow whenever WRITE = 1 and NOT (SEQ = 1, SHADOW = 0) Serial Interface Figure 31 shows the detailed timing diagram for serial interfacing to the AS1543/44. The serial clock provides the conversion clock and also controls the transfer of information to and from the AS1543/44 during each conversion. Figure 31. Serial Interface Timing Diagram CSN tCONVERT SCLK tCSS tCH 1 tCSDOV tCSDOE DOUT Tri-State ADDR3 DIN ADDR2 tDS WRITE SEQ ADDR1 ADDR0 4 ID Bits ADDR3 ADDR2 2 3 4 tDOV DB11 DB10 tDH ADDR1 ADDR0 SE/FDN 5 6 tDOH DB3 DB2 12 13 B 14 tCL DB1 DB0 tDOD DC DC DC DC = Don't Care 15 16 tCSH tQUIET Tri-State www.austriamicrosystems.com Revision 1.00 20 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n The CSN signal initiates the data transfer and conversion process. The falling edge of CSN puts the track and hold into hold mode, takes the bus out of three-state, and the analog input is sampled at this point. The conversion is also initiated at this point and will require 16 SCLK cycles to complete. The track and hold will go back into track on the 14th SCLK falling edge (point B in Figure 31) except when the write is to the shadow register, in which case the track and hold will not return to track until the rising edge of CSN, (point C in Figure 32). On the 16th SCLK falling edge, signal DOUT will go back into tri-state (assuming bit WEAK/TRIN (page 14) is set to 0). Sixteen serial clock cycles are required to perform the conversion process and to access data from the AS1543/44. The 12 bits of data are preceded by the four channel address bits ADDR3:ADDR0 (page 14), identifying which channel the conversion result corresponds to. CSN going low provides address bit ADDR3 to be read in by the microprocessor or DSP. The remaining address bits and data bits are then clocked out by subsequent SCLK falling edges beginning with the second address bit ADDR2; thus the first SCLK falling edge on the serial clock has address bit ADDR3 provided and also clocks out address bit ADDR2. The final bit in the data transfer is valid on the 16th falling edge, having being clocked out on the previous (15th) falling edge. Figure 32. Shadow Register Write Operation Timing Diagram, AS1543 C CSN tCONVERT SCLK tCSS 1 2 3 4 tDOV ADDR1 ADDR0 4 ID Bits VIN2 VIN3 DB11 DB10 tDH VIN4 VIN5 VIN5 VIN6 tCH 5 6 tDOH DB2 13 14 tCL DB1 DB0 tDOD VIN7 Tri-State 15 16 tCSH DOUT tCSDOE ADDR2 tDS VIN0 VIN1 Tri-State ADDR3 DIN Writing information to the control register takes place on the first 13 falling edges of SCLK in a data transfer, assuming the MSB, i.e., bit WRITE (page 14), has been set to 1. If the control register is programmed to use the shadow register, writing of information to the shadow register will take place on all 16 SCLK falling edges in the next serial transfer (see Figure 32). The shadow register will be updated upon the rising edge of CSN and the track and hold will begin to track the first channel selected in the sequence. Note: It is important to note that, if channel 7 (VIN7) is active in the shadow register, 17 clocks will be needed during the programming of the shadow register. CSN will then go high after the 17th clock. In all other cases, 16 clocks will be enough to program the shadow register. If bit WEAK/TRIN (page 14) is set to 1, rather than returning to true tri-state upon the 16th SCLK falling edge, the DOUT signal will instead be pulled weakly to the logic level corresponding to bit ADDR3 of the next serial transfer. This is done to ensure that the MSB of the next serial transfer is set up in time for the first SCLK falling edge after the CSN falling edge. If bit WEAK/TRIN is set to 0 and the DOUT signal has been in true tri-state between conversions, then depending on the particular DSP or microcontroller interfacing to the AS1543/44, address bit ADDR3 may not be set up in time for the DSP/micro to clock it in successfully. In this case, ADDR3 would only be driven from the falling edge of CSN and must then be clocked in by the DSP on the following falling edge of SCLK. www.austriamicrosystems.com Revision 1.00 21 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n However, if bit WEAK/TRIN is set to 1, then although DOUT is driven with address bit ADDR3 since the last conversion, it is nevertheless so weakly driven that another device may still take control of the bus. It will not lead to a bus contention (e.g., a 10 k pull-up or pull-down resistor would be sufficient to overdrive the logic level of ADDR3 between conversions) and all 16 channels may be identified. However, if this does happen and another device takes control of the bus, it is not guaranteed that DOUT will be fully driven to ADDR3 again in time for the read operation when control of the bus is taken back. This is useful if using an automatic sequence mode to identify channel-result pairs. Obviously, if only the first eight channels are in use, then address bit ADDR3 does not need to be decoded, and whether it is successfully clocked in as a 1 or 0 will not matter as long as it is still counted by the DSP as the MSB of the 16-bit serial transfer. Power Modes The AS1543/44 can be operated in 2 different modes: - Normal Mode (see page 22) - Auto Shutdown (see page 23) These modes are designed to provide flexible power management options, and can be selected to optimize the power dissipation and throughput-rate ratio for differing application requirements. The mode of operation of the AS1543/44 is controlled by bits PM1, PM0 (page 14) of the control register. Note: When power supplies are first applied to the AS1543/44, internal power-on reset circuitry sets the device for Auto Shutdown (PM1 = 0, PM0 = x). The AS1543/44 remains in shutdown the first CSN falling edge is received. Normal Mode (PM1 = 1, PM0 = 1) This mode is intended for the fastest throughput rate performance as the user does not have to worry about any power-up times with the AS1543/44 remaining fully powered at all times. Figure 33 shows the operation of the AS1543/44 in normal mode.Conversion is initiated on the falling edge of CSN and the track and hold will enter hold mode. The data presented to pin DIN during the first 13 clock cycles of the data transfer is loaded to the control register (if bit WRITE (page 14) is set to 1). If bit SEQ (page 14) = 0, and bit SHADOW (page 14) = 1 on the previous write, data presented on pin DIN during the first 16 SCLK cycles is loaded into the shadow register. The device will remain fully powered up in normal mode at the end of the conversion as long as bits PM1, PM0 (page 14) are set to 1 in the write transfer during that conversion. To ensure continued operation in normal mode, bits PM1 and PM0 are loaded with 1 on every data transfer. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. The track and hold will go back into track on the 14th SCLK falling edge. Once a data transfer is complete (DOUT has returned to tri-state, bit WEAK/TRIN (page 14) = 0), another conversion can be initiated after the quiet time (tQUIET) has elapsed by bringing CSN low again. Figure 33. Normal Mode Operation CSN SCLK DOUT Channel ID Bits + Conversion Results DIN Data into Control/Shadow Register Notes: 1. Control register data is loaded on the 1st 13 SCLK cycles. 2. Shadow register data is loaded on the 1st 16 SCLK cycles. www.austriamicrosystems.com Revision 1.00 22 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n Auto Shutdown (PM1 = 0, PM0 = X) In this mode, the AS1543/44 automatically enters shutdown after the 14th SLK falling edge of each conversion is updated. When the device is in shutdown mode, the track/hold circuitry is in hold mode. Note: The control register maintains its data while in shutdown mode. Figure 34 shows the operation of the AS1543/44 when it is in automatic shutdown mode The AS1543/44 remains in shutdown until the next CSN falling edge it receives. On this CSN falling edge, the track and hold that was in hold while the device was in shutdown will return to track. Note: Wake-up time from auto shutdown is 1s. Figure 34. Auto Shutdown Mode Operation Device begins to power up on falling CSN edge and remains powered-up on PM1=1 and PM0=1 Device enters shutdown on the 14th SCLK falling edge as PM1 = 0 Device enters automatic shutdown on 14th SCLK falling edge as PM1 = 0 CSN 1 SCLK 14 16 Device is fully powered up Dummy Conversion 1 14 16 1 Valid Conversion 14 16 DOUT Channel ID Bits + Conversion Results Invalid Data Channel ID Bits + Conversion Results DIN Data into Control/Shadow Register Data into Control/Shadow Register Data into Control/Shadow Register Notes: 1. Control register data is loaded on the 1st 13 SCLK cycles. 2. Set control register bits PM1 = 1 and PM0 = 1 to keep the device in normal mode. When running the AS1543/44 with a 20MHz clock, one dummy cycle of 1s (see Figure 34) (16 SCLKs plus Track&Hold aquisation time) should be sufficient to ensure the part is fully powered up. This dummy cycle effectively halves the throughput rate, with every other conversion result being valid. In this mode, the power consumption of the part is greatly reduced with the part entering shutdown at the end of each conversion. Note: The end of shutdown can be controlled by the CSN signal. Power vs. Throughput Rate By operating the AS1543/44 in auto shutdown (see page 23) the average power consumption of the ADC decreases at lower throughput rates. The Power vs. Throughput Rate graph in the Typical Operating Characteristics section shows how as the throughput rate is reduced, the part remains in its shutdown state longer and the average power consumption over time drops accordingly. If the AS1543/44 is operated in a continuous sampling mode with a throughput rate of 100ksps and a SCLK of 20 MHz (VDD = 5V), with bit PM1 (page 14) = 0, i.e., the device is in auto shutdown mode (see page 23), then the power consumption is calculated as follows: The maximum power dissipation during normal operation is 18.4mW (VDD = 5.25V). If the power-up time from auto shutdown is one dummy cycle (i.e., 1s) and the remaining conversion time is another cycle (i.e., 1s) then the AS1543/44 will dissipate approximately 18.4mW for 2s during each conversion cycle. For the remainder of the conversion cycle (8s), the device remains in shutdown mode. The AS1543/44 will dissipate approximately 2.5W for the remaining 8s of the conversion cycle. If the throughput rate is 100ksps, the cycle time is 10s and the average power dissipated during each cycle is: ((2/10) x 18.4mW) + ((8/10) x 2.5W) = 3.682mW (EQ 1) www.austriamicrosystems.com Revision 1.00 23 - 29 AS1543/44 Data Sheet - D e t a i l e d D e s c r i p t i o n The Power vs. Throughput Rate graph in the Typical Operating Characteristics section shows the power vs. throughput rate when using the auto shutdown mode and auto standby mode with 5V supplies (similar power calculations can be done at 3V, althought the power is decreased even more when using 3V supplies). VDRIVE VDRIVE controls the serial interface voltage. VDRIVE allows easy interface to 3V and 5V processors. For example, if the AS1543/44 were operated with a VDD of 5V, pin VDRIVE could be powered from a 3V supply. The AS1543/44 has better dynamic performance with a VDD of 5V while still being able to interface to 3V processors. Note: VDRIVE must not exceed VDD by more than 0.3V (see Absolute Maximum Ratings on page 4) External Reference An external reference source should be connected directly to the pin VREFIN of the AS1543/44. The external reference voltage can reach from 1V to VDD. The correlation between performance of the AS1543/44 and the reference voltage is shown in Figure 9 on page 9. However for specified performance the reference voltage has to stay at 2.5V 1%. The analog input range depends on VREFIN and the setting of bit RANGE and bit SE/FDN of the control register (see Analog Input Configuration on page 15). Errors in the reference source will result in gain errors in the AS1543/44 transfer function and will add to the specified full scale errors of the device. Note: A capacitor of at least 0.1F should be placed on pin REFIN. www.austriamicrosystems.com Revision 1.00 24 - 29 AS1543/44 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 9 Application Information Figure 35 shows a typical connection diagram for the AS1543/44. In this configuration, pin AGND, GND and DGND connected to the analog ground plane of the system. In Figure 35, REFIN is connected to a decoupled 2.5V reference source, to provide an analog input range of 0 to 2.5V (if RANGE (page 14) is 1 and bit SE/FDN (page 14) = 1) or 0 to 5V (if bit RANGE is 0 and bit SE/FDN = 1). In Figure 35 the AS1543/44 is connected to a VDD of 5V, however the serial interface is connected to a 3V microprocessor. Pin VDRIVE is connected to the same 3V supply of the microprocessor to allow a 3V logic interface. The conversion result is output in a 16-bit word. This 16-bit data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data. Note: For applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance (see Power Modes on page 22). Figure 35. Typical Application 5V VDD 0.1F 10F GND 0V to VREFIN DOUT DSP/P SCLK VIN0:3/7 AS1543/44 DIN CSN 2.5V REFIN 4.7F AGND DGND VDRIVE 0.1F 10F 3V Note: For the circuit shown in Figure 35, unused input channels should be connected to ground. For optimum performance decouple all analog input channels and the reference input voltage to the ground of AGND. Initialisation When power is first applied to the AS1543/44 interal power-on reset circuitry sets the device for Auto Shutdown (PM1 = 0, PM0 = X) on page 23. Note: The device requires 10s after the power supplies stabilize; no conversions should be initiated during this time. The digital output at pin DOUT will be set to tri-state after internal power-on reset. www.austriamicrosystems.com Revision 1.00 25 - 29 AS1543/44 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Grounding and Layout Considerations The AS1543/44 has excellent immunity to noise on the power supplies as can be seen by the PSRR vs. Supply Signal Frequency graph on page 11, however, the following should be considered regarding grounding and PCB layout: - The PCB should be designed such that the analog and digital sections are confined to separate areas of the board. This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. - Pins AGND and GND should be tied to the analog ground plane. Pin DGND should be tied to the digital ground plane. - Digital and analog ground planes should be joined at only one place. If the AS1543/44 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point - a star ground point which should be established as close as possible to the AS1543/44. - Avoid running digital lines under the device as these will couple noise onto the die. - The analog ground plane should be allowed to run under the AS1543/44 to avoid noise coupling. - The power supply lines to the AS1543/44 should use as large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power supply line. - Fast-switching signals (e.g., clocks) should be shielded with digital ground to avoid radiating noise to other sections of the PCB. - Clock signals should not be run near the analog inputs. - Avoid crossover of digital and analog signals. - Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. - All analog input channels and the reference input voltage should be decoupled to the ground pin of AGND. - All analog supplies should be decoupled with 10F tantalum in parallel with 0.1F capacitors to GND. To achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1F capacitors should be low ESR and ESI (e.g., common ceramic or surface mount types) which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. www.austriamicrosystems.com Revision 1.00 26 - 29 AS1543/44 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 10 Package Drawings and Markings The device is available in an TQFN(4x4)-20 package. Figure 36. TQFN(4x4)-20 Package Symbol A A1 A3 L1 aaa bbb ccc ddd Min 0.70 0.00 0.03 Typ 0.75 0.02 REF 0.10 0.10 0.10 0.05 Max 0.80 0.05 0.15 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 Symbol D BSC E BSC D2 E2 L b e N ND Min 2.00 2.00 0.45 0.18 Typ 4.00 4.00 2.15 2.15 0.55 0.25 0.5 20 5 Max 2.25 2.25 0.65 0.30 Notes 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 5 1, 2 1, 2, 5 Notes: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters, angle is in degrees. N is the total number of terminals. Terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the area indicated. The terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. ND refers to the maximum number of terminals on D side. 7. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. www.austriamicrosystems.com Revision 1.00 27 - 29 AS1543/44 Data Sheet - O r d e r i n g I n f o r m a t i o n 11 Ordering Information The device is available as the standard products shown in Table 14. Table 14. Ordering Information Model AS1543-BTST AS1544-BTST Marking AS1543 AS1544 Description 8-Channel, 1 Msps, 12-Bit ADC with Sequencer 4-Channel, 1 Msps, 12-Bit ADC with Sequencer Delivery Form Tape and Reel Tape and Reel Package TQFN(4x4)-20 TQFN(4x4)-20 www.austriamicrosystems.com Revision 1.00 28 - 29 AS1543/44 Data Sheet Copyrights Copyright (c) 1997-2008, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered (R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or lifesustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact-us www.austriamicrosystems.com Revision 1.00 29 - 29 |
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